First Board Walkthrough

1. Describe the circuit

Choose New project, select Schem, and send a brief such as:

If the assistant asks for continue, finish the discussion before requesting the build. The circuit plan is included in generation. Confirm your email address if the application asks before starting a run.

2. Inspect and approve the schematic

Read the real schematic in the viewer. Check Components, Requirements and Issues. Ask questions or apply a correction proposal if needed. Review schematic gives a paid assistant assessment; you still click Approve schematic yourself.

3. Configure the physical board

Select Board. In Manufacturing, choose the board house, size goal and copper-layer policy, inspect its rules, and click Save. In Placement & routing, choose ordinary routing effort and time cap and save. The example's explicitly requested two layers remain fixed unless you edit that requirement.

4. Place, route and inspect the result

Click Place & Route on Board. Follow progress in the thread and status bar. The result opens on Route. Check remaining connections and DRC findings; elapsed time depends on circuit complexity, placement work and the chosen routing settings.

5. Choose the next action and download

Use ordinary Route / Re-route on Board to retain placement. For a stuck route, configure When escalating on Route and choose Try harder or Rethink placement. When verification permits export, open Files and download the full bundle, Gerbers, drills and assembly data.

Workspace & Navigation

• Top bar: Current project and revision, account balance, Buy tokens, Guide, Inspector and Sign out. Admin appears for accounts that have access.
• Left rail: Schem, Board and Route. The schematic dot shows unreviewed, approved or review-invalidated state.
• Left sidebar: Projects, Layers, Objects, Nets and Parts, plus the revision history. Click a panel heading to collapse or expand it.
• Canvas: KiCanvas renders the generated KiCad file. Use its pan, zoom, fit and selection tools. Click a component for properties; the inspector echoes the selection.
• Conversation/inspector: Messages, review/proposal cards, approval and run buttons, current-view settings, requirements, issues and last-change details. Drag its left edge to resize; Inspector toggles visibility.
• Status bar: Current revision, parts, nets, DRC, active work and cumulative project spend/cap.

Document and visibility controls

The canvas toolbar identifies the file on screen. Open file opens it in a new tab; Reload rereads artifacts; Files lists downloads. Redraw appears for a stale schematic and redraws the current circuit. It is a deterministic drawing action, not another circuit-generation request.

The Layers panel changes copper visibility/dimming. Objects and Nets expose references and connection names for precise discussion. The PCB routed-connections legend is hidden over a schematic, where it would describe a different document.

Keyboard and guide navigation

Enter sends; Shift + Enter inserts a newline. Outside text fields, 1–3 switch views. In the guided tour, use the topic menu, Back/Next, ←/→ or Esc. Closing the tour restores your previous workspace view.

Projects & Revisions

Open Projects or click the project name in the top bar to switch designs. New project opens a blank workspace; the first message creates the project. Rename and Archive are shown on the current project's card.

Inspect history without reverting

Each published change creates a revision. View displays that revision's own files without changing the head. A banner identifies the historical view; Back to current restores the current files.

Return to an earlier design

Go to moves the project head to the selected revision. Later work branches from it, and newer revisions remain in history. This is different from simply viewing an old drawing. Check the current revision before applying another change.

Last change compares the head to its parent and lists additions, removals, changed objects and untouched content. A failed build does not publish a new head, so the last successful revision remains available.

Briefs, Imports & Edits

Information to include in a brief

• Purpose, input sources, output loads and required controls.
• Supply voltage, current, power budget and signal interfaces.
• Required ICs/modules and exact package variants when important.
• Through-hole/SMD preference, board size, copper layers and manufacturer.
• Connector accessibility, mounting, heatsink separation and RF keepouts.

Questions and changes have different effects

Ask why a component is needed or what an issue means to get an explanation. To change a built circuit, name references/nets and use the scope chip to confirm the intended layer. A proposal shows the changes, warnings, untouched content and rebuild requirements; choose Apply or Discard.

A proposal that explicitly says a re-place or reroute follows will start that work after Apply. Read the follow-up line, especially when placement must stay fixed. Conversational summaries alone are not proof that an edit or build has completed; use the proposal, revision and generated files.

Import your existing circuit

The paperclip accepts .kicad_sch schematics and supported .net/.xml netlists. The imported circuit becomes a proposal. Review component/package findings, apply it, inspect the resulting schematic and approve before layout.

Parts, Packages & BOM

The Parts sidebar searches package geometry available to the builder. A kind selection seeds the query. Search by package, pitch or connector type, pin results for the next request, and manage the chosen list above the composer.

Include supply details adds supplier information and is a paid lookup. Use its sources and ordering identity alongside the package. A footprint's dimensions do not establish an IC's pin functions, ratings or exact ordering variant.

Identity checks during generation

The builder checks installed symbol identities, complete pin coverage and compatible footprints. Incorrect package selections receive a bounded correction attempt with library evidence. If a required component cannot be represented with available CAD, resolve the limitation or revise the component choice explicitly.

Components and external modules

On Schem, Components lists quantities, references, values, packages and available MPNs. A header labelled MIC_IN or Bluetooth is an interface for external hardware, not the microphone capsule or radio electronics on this PCB. Specify direct mounting when that is required.

The generated BOM includes additional cooling and mounting hardware when assigned. The full bundle carries available project-local libraries and models so the design can be opened on another machine.

Requirements & Approval

The Requirements checklist is derived from the request. It checks functions a plausible-looking drawing might omit: a PD controller, processing circuitry, an indicator, supply nets or other requested capabilities.

• Met: The current design has matching evidence.
• Missing: A required function is absent.
• Unverifiable: The predicate or installed evidence cannot establish the claim.
• Manual: A person must decide, for example acoustic performance or enclosure fit.
• Unchecked: There is no built design to assess.

Critical machine-checkable requirements block schematic publication when missing or unverifiable. Generic op-amp requirements use installed component capability and connected pins, while explicitly requested ICs stay exact choices. Industry context can add sourced considerations; its links identify the evidence.

Review versus approve

Review schematic and Review PCB make paid assistant assessments. They can explain issues or suggest fixes; fixes have an apply step. Approve schematic is your separate review decision and is required before placement/routing.

An edit affecting reviewed circuitry invalidates approval. Use Re-approve after checking it, or Re-open for editing to remove approval yourself. Approval records a reviewed revision; it is separate from fabrication verification.

Manufacturing Settings

Open Board → Manufacturing in the inspector. This panel describes the physical board: board house, size goal, copper layers and manufacturing limits.

Board house and saving

Select a listed profile, such as Generic, JLCPCB or PCBWay, and read its notes and Published capabilities link. Profiles have different minimum geometries and can have a different tier for four or more copper layers.

Switching the house previews its rules and clears the previous house's overrides. Click Save to persist changes. Settings chosen before a project exists are held for the first project created in that workspace. With a project open, settings are per project.

Board size

• As the parts need: Derive an automatic outline from the placement.
• As small as still routes: Start compact, compare trial routes, and retain the smallest fully routed candidate or the candidate with fewer opens if none finishes. If placement lacks space, measured overlap, clearance, cooling and reserved-area deficits guide enlargement and renewed checking.
• Explicit dimensions: A fixed outline in the design is retained. Request a reviewed outline change when it needs to grow; the size-goal dropdown does not erase that requirement.

Copper layers

Automatic — use 4 if 2 will not route permits an eligible two-layer design to try four within the run's routing time cap. It also applies to ordinary Place & Route and Route runs. More layers can raise manufacturing cost. A layer count explicitly stated in the request or design is retained. Fixed retains the current count.

Rules and overrides

Expand Rules. A blank input inherits the house's value shown as its placeholder; an entered value is a project override. All dimensional fields use the displayed units. The panel identifies the active layer tier.

• Track and clearance: Minimum trace width and copper spacing.
• Vias: Minimum drill, pad diameter and annular ring.
• Holes: Plated-hole annular ring, minimum/maximum drilled hole and hole-to-hole spacing.
• Edges and silkscreen: Copper-to-edge clearance, minimum text height/line width and silk-to-pad spacing.
• Capacity: Maximum layers and minimum/maximum board width and height.

Clear overrides empties custom inputs; save afterward to restore the profile values. Rejected values are explained by the save response. Save changes before the next run; existing copper is not rebuilt by saving alone.

Placement & Routing

Open Board → Placement & routing. Save the ordinary run settings here before pressing the layout buttons.

• Placement engine: Shown when alternatives are available on the server. It controls placement reasoning; routing-only runs do not reposition parts.
• Routing effort: Low: 10 passes; Standard: 25; High: 50; Maximum: 100.
• Time cap: 5, 10, 20 or 30 minutes of routing work. Placement computation does not consume the time reserved for router trials; overall job time also includes other stages and verification.

All layout actions require schematic approval. Routing-only and escalation actions also require current placement. A changed part or footprint can make placement stale, requiring re-placement; disabled controls show the reason.

How placement is evaluated

Placement considers courtyard overlap, connector access, thermal spacing, named constraints, keepouts, pin escape, path obstructions and crossing-net pressure. Compact sizing additionally compares actual trial routes. More space is added only after assessed geometry needs it, and the resulting candidate is checked again.

Ordinary runs are bounded by effort/time and the Manufacturing layer policy. Narrow-track and crossing-link escalation permissions are forced off for these runs. Some verification, direct same-net repair and permitted layer trials can still occur; the ordinary action is not a request for the full paid ladder.

The Escalation Ladder

When a placed board still has open connections, open Route → When escalating. These settings apply to Try harder and Rethink placement, with a separate escalation time cap.

The controls

• Narrow a net that will not fit: Allowed enables limited thinner-track retries. Never leaves the connection open instead. Narrowing respects manufacturer minimums and applicable current/temperature-rise limits; concessions are reported.
• Crossing links: Allowed permits a compatible physical 0Ω bridge, or a manually soldered wire bridge where no part fits. Never disables both.
• Time cap: 5, 10, 20 or 30 minutes for one escalated run's routing work. The eligible rungs share the budget; each does not get a fresh full cap.
• Copper layers: Permission to change layers is set in Manufacturing, not in this panel, and can apply to ordinary runs too.

Try harder: routing on existing placement

Try harder calls no model. It works through applicable tactics, keeping candidates only when the routing/geometry checks accept an improvement:

1. Narrow tracks: Free a pad or passage within permitted copper/current limits.
2. Component crossing links: Insert compatible 0Ω bridges when links are allowed and room exists.
3. Eligible extra layers: Try a four-layer arrangement when Manufacturing and the stated design permit it. Existing multilayer boards may also try freeing an inner routing layer.
4. Routing alternatives: Try applicable via choices and router seeds within the remaining budget.
5. Direct copper ties: Close an unobstructed same-net connection when the resulting copper passes checks.
6. Wire bridges: Try hand-soldered links last when allowed, with assembly instructions.

This is an eligibility ladder, not a promise that every rung will execute. It may stop when routing is complete or skip a rung because of permissions, ratings, geometry, fixed layers or remaining time. Progress and reports explain which options helped or were refused. Ground/power-plane repair and verification can accompany the attempts.

Rethink placement: model-assisted candidates

If component arrangement is the blocker, Rethink placement asks a model to propose moves, evaluates their routed results and retains an accepted candidate. This spends model tokens and router time and can change placement, so inspect Last change and the new revision. Stated placement constraints, keepouts and crossing-net checks remain part of acceptance.

Read the assembly consequences

Crossing links add assembly work and can add BOM entries. assembly.txt identifies links; wire bridges are also marked on silkscreen. More copper layers change the physical board and can increase its fab price. Review these results before ordering.

Progress & Troubleshooting

The conversation shows the run's current stage, messages, spend and result. The status bar shows active work even after a reload. Use Cancel when offered; a stopped run with a resumable checkpoint offers a resume action in the thread.

Reading results

The PCB legend counts routed connections. One net can require several connections, and one trace on a net does not mean the entire net is finished. Ground-pour connectivity is verified against actual copper. Issues name errors/warnings, affected references/nets and available explanations.

A job can finish with opens or warnings. Treat the recorded verification and fabrication status separately from job state. Correct the named cause before retrying; a failed job keeps the last published revision.

Widths, Current & Impedance

Name rails and their expected voltage/current in the brief. The design records net roles, classes, widths, via geometry and power budgets. Minimum fabrication width and a width adequate for the intended current are different constraints.

For impedance-controlled signals, state the target, reference plane and stackup information. Ask for the assumptions and verify the generated class/geometry in KiCad against the manufacturer's dielectric stackup. A generic board-house profile does not establish an exact impedance or guarantee controlled-impedance fabrication.

Escalated narrowing uses applicable rail current/temperature limits and never intentionally goes below the house minimum. Review reported concessions instead of assuming the originally requested width exists everywhere.

Differential Signals

Use clear names such as USB_DP/USB_DM and state the interface, speed, impedance target and any length/skew requirement. Inspect the generated roles, pin mapping and breakout corridor rather than relying on the names alone.

The placement/routing checks preserve declared breakout channels and keepouts. Their capacity and pin-escape checks establish necessary conditions, not a completed route. Inspect actual copper and verify pair spacing, reference continuity and matching in KiCad; the automatic route is not a guarantee of phase or length matching.

Cooling & Heatsinks

For power BJTs, MOSFETs, amplifiers and regulators, describe expected device loss, current, supply voltage, ambient temperature and mounting constraints. Amplifier output watts are not the same as device heat dissipation.

Supported power packages receive automatic cooling plans and corresponding placement envelopes. Suitable package-mounted heatsinks and insulated mounting hardware are included in generated assembly data. Small-signal devices are excluded; surface-mount power packages can use PCB heat spreading, while unsupported mounting arrangements are reported.

Download heatsink-plan.json and thermal-assembly.md when present. Review selected geometry, loss assumptions, mounting insulation and any missing thermal data. A heatsink footprint proves fit geometry, not a verified thermal rating. Named separation constraints remain distinct from the full heatsink envelope clearance.

For exposed-pad cooling or thermal vias, inspect the correct pad/net assignment and actual exported copper. Keep RF antenna regions and declared copper keepouts clear on their required layers.

Files & Fabrication

Open Files above the canvas or use links attached to the producing message. Individual files and an Everything (.zip) bundle are available when the run generated them. Prefer the full bundle when transferring the project to another machine.

• Schematic build: KiCad schematic, SVG preview, design/netlist files and applicable thermal plans.
• Board build: PCB and project files, BOM, placement data, router files and available assembly instructions.
• Portable CAD: Available project-local symbol/footprint data and 3D models in the full bundle; missing models are reported.
• Fabrication-ready output: Gerber/drill artifacts after authoritative routing/DRC and required package verification permit export.

Fabrication files are produced by the eligible build/export stages. A chat request to generate them does not bypass verification. If export is withheld, read Issues, package findings and remaining connections, correct them and run the appropriate layout action.

Check the bundle's revision against the drawing reviewed. For crossing links, read assembly.txt and the BOM; hand-soldered bridges require manual assembly. Open the full KiCad project to inspect models and final copper before handing files to your board house.

Balance & Spend Caps

The account balance appears in the top bar. Buy tokens offers the configured top-up options. Model conversations, generation, reviews, requirement extraction and supply-detail searches can spend tokens; routing spends compute as well.

Project cap versus routing time cap

The bottom spend line shows cumulative project spend. Click it to set a cap; enter an empty value to remove the cap. A project cap applies across its work. The ordinary and escalation time caps limit router work for individual runs and are separate from the monetary/token spend cap.

Admission checks the account balance and project cap against estimated cost before starting. Usage is metered from actual model/router work. Follow progress and spend in the thread; a stopped or refused action gives a reason. If the account cannot cover a run or a project cap is exhausted, top up or adjust the cap before retrying.

Viewing files, switching views and the guided tour do not start a model or router run. The tour's example button fills an empty composer and leaves sending to you.